14 Pages, 328 KB, Original
CPLD, 128-Macrocell MAX
21 Pages, 205 KB, Original
CPLD MAX® Family 2.5K Gates 128 Macro Cells 40MHz 0.65um Technology 5V 68-Pin LCC
21 Pages, 205 KB, Original
CPLD MAX® Family 2.5K Gates 128 Macro Cells 40MHz 0.65um Technology 5V 68-Pin LCC
21 Pages, 205 KB, Original
CPLD MAX® Family 2.5K Gates 128 Macro Cells 40MHz 0.65um Technology 5V 68-Pin LCC
21 Pages, 205 KB, Original
Programmable Logic Arrays 68-Pin LCC
21 Pages, 205 KB, Original
PROG. LOGIC DEVICE, UV ERASABLE, 128-MACROCELL, 35 NS DELAY TIME