STP12NM50FP STB12NM50 - STB12NM50-1 N-channel 550V @ tjmax - 0.30 - 12A TO-220/FP/D2/I2PAK MDmeshTM Power MOSFET General features Type VDSS (@Tjmax) RDS(on) ID STB12NM50 550V <0.35 12A STB12NM50-1 550V <0.35 12A STP12NM50 550V <0.35 12A STP12NM50FP 550V <0.35 12A High dv/dt and avalanche capabilities Low input capacitance and gate charge 100% avalanche tested Low gate input resistance Tight process control and high manufacturing yields 3 1 3 2 1 TO-220 TO-220FP 3 3 12 1 DPAK 2 IPAK Internal schematic diagram Description The MDmeshTM is a new revolutionary MOSFET technology that associates the Multiple Drain process with the Company's PowerMESHTM horizontal layout. The resulting product has an outstanding low on-resistance, impressively high dv/dt and excellent avalanche characteristics. The adoption of the Company's proprietary strip technique yields overall dynamic performance that is significantly better than that of similar competition's products. Applications Switching applicatio

STP12NM50FP STB12NM50 - STB12NM50-1 N-channel 550V @ tjmax - 0.30 - 12A TO-220/FP/D2/I2PAK MDmeshTM Power MOSFET General features Type VDSS (@Tjmax) RDS(on) ID STB12NM50 550V <0.35 12A STB12NM50-1 550V <0.35 12A STP12NM50 550V <0.35 12A STP12NM50FP 550V <0.35 12A High dv/dt and avalanche capabilities Low input capacitance and gate charge 100% avalanche tested Low gate input resistance Tight process control and high manufacturing yields 3 1 3 2 1 TO-220 TO-220FP 3 3 12 1 DPAK 2 IPAK Internal schematic diagram Description The MDmeshTM is a new revolutionary MOSFET technology that associates the Multiple Drain process with the Company's PowerMESHTM horizontal layout. The resulting product has an outstanding low on-resistance, impressively high dv/dt and excellent avalanche characteristics. The adoption of the Company's proprietary strip technique yields overall dynamic performance that is significantly better than that of similar competition's products. Applications Switching applicatio

STP12NM50FP STB12NM50 - STB12NM50-1 N-CHANNEL 550V @ Tjmax-0.30 - 12A TO-220/FP/D/IPAK MDmeshTM Power MOSFET Table 1: General Features Figure 1: Package TYPE VDSS (@Tjmax) RDS(on) ID STB12NM50 STB12NM50-1 STP12NM50 STP12NM50FP 550V 550V 550V 550V < 0.35 < 0.35 < 0.35 < 0.35 12A 12A 12A 12A TYPICAL RDS(on) = 0.30 HIGH dv/dt AND AVALANCHE CAPABILITIES LOW INPUT CAPACITANCE AND GATE CHARGE 100% AVALANCHE TESTED LOW GATE INPUT RESISTANCE TIGHT PROCESS CONTROL AND HIGH MANUFACTURING YIELDS DESCRIPTION The MDmeshTM is a new revolutionary MOSFET technology that associates the Multiple Drain process with the Company's PowerMESHTM horizontal layout. The resulting product has an outstanding low on-resistance, impressively high dv/dt and excellent avalanche characteristics. The adoption of the Company's proprietary strip technique yields overall dynamic performance that is significantly better than that of similar competition's products. 3 3 1 TO-220 2 1 2 TO-220FP 3 12 1 D2PAK 3 I2PAK Figure 2

STP12NM50FP STB12NM50 - STB12NM50-1 N-CHANNEL 550V @ Tjmax-0.30 - 12A TO-220/FP/D/IPAK Zener-Protected SuperMESHTMMOSFET Table 1: General Features TYPE STB12NM50 STB12NM50-1 STP12NM50 STP12NM50FP VDSS (@Tjmax) 550 V 550 V 550 V 550 V Figure 1: Package RDS(on) < 0.35 < 0.35 < 0.35 < 0.35 ID 12 A 12 A 12 A 12 A TYPICAL RDS(on) = 0.30 HIGH dv/dt AND AVALANCHE CAPABILITIES LOW INPUT CAPACITANCE AND GATE CHARGE 100% AVALANCHE TESTED LOW GATE INPUT RESISTANCE TIGHT PROCESS CONTROL AND HIGH MANUFACTURING YIELDS DESCRIPTION The MDmeshTM is a new revolutionary MOSFET technology that associates the Multiple Drain process with the Company's PowerMESHTM horizontal layout. The resulting product has an outstanding low on-resistance, impressively high dv/dt and excellent avalanche characteristics. The adoption of the Company's proprietary strip technique yields overall dynamic performance that is significantly better than that of similar competition's products. 3 3 1 TO-220 2 1 2 TO-220FP 3 12 1 D2

STP12NM50FP STB12NM50 - STB12NM50-1 N-CHANNEL 500V - 0.30 - 12A TO-220/FP/D2PAK/I2PAK MDmesh Power MOSFET TYPE STP12NM50/FP STB12NM50 STB12NM50-1 VDSS R DS(on) ID 500V 500V 500V <0.35 <0.35 <0.35 12 A 12 A 12 A TYPICAL RDS(on) = 0.30 HIGH dv/dt AND AVALANCHE CAPABILITIES 100% AVALANCHE TESTED LOW INPUT CAPACITANCE AND GATE CHARGE LOW GATE INPUT RESISTANCE TIGHT PROCESS CONTROL AND HIGH MANUFACTURING YIELDS DESCRIPTION The MDmesh is a new revolutionary MOSFET technology that associates the Multiple Drain process with the Company's PowerMESH horizontal layout. The resulting product has an outstanding low on-resistance, impressively high dv/dt and excellent avalanche characteristics. The adoption of the Company's proprietary strip technique yields overall dynamic performance that is significantly better than that of similar competition's products. 3 2 1 TO-220 TO-220FP 3 1 1 D2PAK 2 3 I2PAK (Tabless TO-220) INTERNAL SCHEMATIC DIAGRAM APPLICATIONS The MDmesh family is very suitable for increasing pow

22 220PF R26 240K R15 150K C11 10NF C13 1uF C14 100NF 7 6 5 4 3 2 1 C10 1N0 L6563 R27 470 PFC_OK TBO VFF CS MULT COMP INV U1 8 5 1 8 9 10 11 12 13 R89 100K + R20 0R0 R21 27R C15 22uF R100 0R0 C16 1N0 C39 100NF R54 0R0 0R0 R101 R22 0R47 R46 100K Q1 R19 56K STP12NM50FP R23 0R47 + R99 15K C48 6.8NF D27 LL4148 C49 330PF U5B PC817 3 4 C47 2.2NF C5 470NF 400V 4 10NF U3B PC817 C52 100NF 8 7 6 5 3 2 1 R71 10R C17 N.M. D21 1N4148 220PF C41 4N7 D22 LL4148 C40 10NF R70 33R R78 19K6 C43 C45 220K R98 L2 700uH 3 10 5 8 4 14 R80 1K0 PWM_LATCH PWM_STOP RUN ZCD GND GD VCC C3 2N2 - + 88 - 264Vac L1 86A-5163 D29 LL4148 C1 470nF 4 3 D3 1N4005 PFC_STOP COMP VREF OSC SS ISEN DIS LINE U2 L6591 R84 220R Vcc LVG GND N.C. FGND HVG BOOT 9 10 11 12 13 14 15 R9 82K 2 N.M. + C51 22uF R77 56R D24 LL4148 R75 56R D23 LL4148 R72 10R R74 10R + R53 0R0 R3 680K Q3 STP12NM50FP C57 100uF D26 STPS1L60A R81 0R82 R79 100K R17 0R0 R82 0R82 C44 220NF Q4 250V STP12NM50FP R73 100K R28 24K9 R13 8.2K R12 3M0 R8 680K R

STP12NM50FP STB12NM50 - STB12NM50-1 N-CHANNEL 500V - 0.30 - 12A TO-220/FP/D2PAK/I2PAK MDmeshTMPower MOSFET TYPE STP12NM50/FP STB12NM50 STB12NM50-1 VDSS RDS(on) ID 500V 500V 500V <0.35 <0.35 <0.35 12 A 12 A 12 A TYPICAL RDS(on) = 0.30 HIGH dv/dt AND AVALANCHE CAPABILITIES 100% AVALANCHE TESTED LOW INPUT CAPACITANCE AND GATE CHARGE LOW GATE INPUT RESISTANCE TIGHT PROCESS CONTROL AND HIGH MANUFACTURING YIELDS DESCRIPTION The MDmeshTM is a new revolutionary MOSFET technology that associates the Multiple Drain process with the Company's PowerMESHTM horizontal layout. The resulting product has an outstanding low on-resistance, impressively high dv/dt and excellent avalanche characteristics. The adoption of the Company's proprietary strip technique yields overall dynamic performance that is significantly better than that of similar competition's products. 3 1 TO-220 2 TO-220FP 3 12 1 D2PAK 3 I2PAK (Tabless TO-220) INTERNAL SCHEMATIC DIAGRAM APPLICATIONS The MDmeshTM family is very suitable for increasin

100nF C30 330R 10R R18 NC R45 1.8k 510R 24k R17 1k R19 24k R51 1k R53 R20 DRV C32 100nF L1 67uH R44 D1 MUR160 MMSD4148 D8 MMSD4148 220pF/630Vdc D9 Heatsink for sync rect: 1.2k C7 15nF/630V D10 C48 C6 15nF/630V MURS160 R22 13 14 15 16 17 18 19 20 22 23 24 STP12NM50FP 1N5408 D3 STP12NM50FP MURS160 L2 12 11 10 9 8 7 VCC C54 3.9nF R75 27R Rsense Q6 BC848B VCC C43 100nF ? 4.7uF/25V C1 3k R21 6 1 T2 R74 27R 1 L7 1 L8 Q5 Q4 Q8 BC848B ON/OFF PGout Vref ISO4 SFH6156-2 Relay C49 1nF R76 27R R73 27R IRFB3206 IRFB3206 C53 3.9nF R16 47k R15 47k NC C51 ISO3 SFH6156-2 R50 1k U3 TL431 5.6k R62 NC R69 R82 22R R80 22R 10k C57 R78 0R 1k 30k 24k C52 22nF C21 1k 30k 24k 100nF R54 R63 8.2k R89 R86 R85 R90 R84 R83 C56 100nF R79 0R C20 1uF 1 2 3 4 C55 1uF 1 2 3 4 C58 R60 1k G G 10R R68 C24 DRV GND COMP CS DRV GND COMP CS house-keeping 1k SW1 SW LED1 Green LED R57 LED2 Green LED 510R 5.1k C25 PGI for R65 8.2k R56 C22 Vcc MIN_TOFF MIN_TON TRIG U5 NCP4303A R87 0R Vcc MIN_TOFF MIN_TON TRIG U6 NCP4303A R88 0R R

70nF-630V C7 330uF-450 V +400Vdc +400Vdc NC RTN RTN +400Vo ut R3 100K R5 4 7R +400Vdc R9 R10 510k 510k R4 100K R102 C10 22N D4 LL4 148 0R0 R11 D5 510k R12 C13 22 0nF C11 C12 470nF/50V 100uF/50V BZX85-C18 R13 47K R36 3R9 12k C14 2.2uF R14 47k D7 LL41 48 Q1 STP12NM50FP 1 INV VCC COMP GD MULT GND CS ZCD 2 R17 6R8 8 7 L65 62A 3 R35 3R9 LL41 48 D6 6 C15 68pF D8 LL4148 Q2 STP12NM50FP 4 5 R18 6R8 R15 1k8 R31 3k C16 120p F R1 6 3 0k R19 1K0 R32 R33 620k 620k Q3 BC857C C20 R34 C21 10k 10nF 330 pF R101 0R0 6/24 R20 R21 0R47-1 W 0R4 7-1W R22 0R47-1W R23 0R4 7-1W AN2755 Test results and significant waveforms 2 Test results and significant waveforms 2.1 Harmonic content measurement One of the main purposes of a PFC pre-conditioner is the correction of input current distortion, decreasing the harmonic contents below the limits of the actual regulations. Therefore, the board has been tested according to the European rule EN61000-3-2 class-D and Japanese rule JEIDA-MITI class-D, at full load and 70

ine voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Figure 9. The effect of fixing off-time - boundary between DCM and CCM . . . . . . . . . . . . . . . . . . . . 16 Figure 10. Conduction losses and total losses in the STP12NM50FP MOSFET couples for the 400W FOT PFC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Figure 11. L6564 internal schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Figure 12. Open loop transfer function-bode plot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Figure 13. Phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Figure 14. Multiplier characteristics family for VFF =1 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Figure 15. M

ine voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Figure 9. The effect of fixing off-time - boundary between DCM and CCM . . . . . . . . . . . . . . . . . . . . 16 Figure 10. Conduction losses and total losses in the STP12NM50FP MOSFET couples for the 400W FOT PFC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Figure 11. L6564 internal schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Figure 12. Open loop transfer function-bode plot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Figure 13. Phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Figure 14. Multiplier characteristics family for VFF =1 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Figure 15. M

-630V 1 2 3 4 5 C7 330uF-450V +400Vdc +400Vdc NC RTN RTN +400Vout R3 100K R5 47R +400Vdc R9 R10 510k 510k R4 100K R102 C10 22N 0R0 D4 LL4148 R11 D5 BZX85-C18 510k R12 C13 220nF C11 C12 470nF/50V 100uF/50V R13 47K R36 3R9 12k C14 2.2uF R14 47k D7 LL4148 Q1 STP12NM50FP 1 2 3 4 INV VCC COMP GD MULT GND CS ZCD L6562A R17 6R8 8 7 R35 3R9 LL4148 D6 6 C15 68pF D8 LL4148 Q2 STP12NM50FP 5 R18 6R8 R15 1k8 R31 3k C16 120pF R16 30k R19 1K0 R32 R33 620k 620k Q3 BC857C C20 R34 C21 10k 10nF 330pF R101 0R0 2/9 Boost inductor spec. (Delta Electronics 86H-5410B): - vertical 6+6, PQ40+30 ferrite - 1 mm gap for 500 H primary inductance - Primary: 65 turns 30x0.2 mm - Secondary: 5 turns 0.28 mm R20 R21 0R47-1W 0R47-1W R22 0R47-1W R23 0R47-1W EVL6562A-400W 2 Circuit layout Circuit layout Figure 2. PCB layout(a) PFC PRECONDITIONER USING L6562A FOT a. Not in scale 3/9 Typical performance EVL6562A-400W 3 Typical performance Figure 3. EVL6562A-400W compliance to EN61000-3-2 standard @full load Measurements @

C13 2nF2-Y 2 C11 680nF-X2 C4 - + PWM-Latch 220pF C17 Vaux DM-51uH-6A 15k R17 3k3 R14 100pF C15 470nF/630V C5 L3 LL4148 D5 CS 470nF/630V C6 1k0 R19 6R8 LL4148 R18 6R8 D6 LL4148 R15 330pF C18 5-6 D4 0R39 R21 1N5406 PQ40-500uH L4 D1 1-2 0R39 R22 0R39 R23 Q1 STP12NM50FP STTH8R06 D3 NTC 2R5-S237 R2 0R39 R24 Q2 STP12NM50FP 470nF/630V C7 2nF2-Y 1 C9 C8 330uF/450V Vdc +400V Figure 1. 1 J1 D2 D15XB60 Vrect Main characteristics and circuit description AN2509 signal ST-BY present), the PFC and resonant converter will not operate, and only +5 V and +3.3 V supplies are available on the output. In order to enable the +200 V and +75 V outputs, Pin 9 of Connector J3 must be pulled down to ground. PFC pre-regulator electrical diagram PWM-Latch LINE 10 R42 16k R41 2M2 R37 270pF C26 470nF C24 100nF C23 4nF7 C33 2k7 R34 Q12 BC557 1k5 220R R87 470nF C60 10k 1k5 R54 R47 R46 560k R88 R36 0R GND LINE SFH617A-2 U3B 10nF C40 PFC-STOP LVG DIS VCC ISEN NC OUT HVG VBOOT STBY RFMIN CF DELAY CSS U2 L6599 C27 100n

XB60 R15 3K3 R101 0R0 LL4148 D6 470nF-630V C5 D4 LL4148 R4 180K R3 180K 8 5-6 330pF C20 R18 6R8 R35 3R9 R17 6R8 R36 3R9 D5 BZX85-C15 C10 18N R5 47R 1K0 R19 11 L4 PQ40-500uH 1-2 D8 LL4148 D7 LL4148 R20 0R39-1W R21 0R39-1W +400Vdc R22 0R39-1W R23 0R39-1W Q2 STP12NM50FP C7 330uF-450V NTC 2R5-S237 R2 470nF-630V C6 Q1 STP12NM50FP STTH8R06 D3 1N5406 D1 J2 +400Vdc +400Vdc NC RTN RTN +400Vout 1 2 3 4 5 Figure 1. 2 8A/250V CM-1.5mH-5A JP101 JUMPER 1 1 J1 F1 1 Features EVAL6563-400W Features EVAL6563-400W schematic EVAL6563-400W Features Main characteristics and circuit description: Table 1. Line voltage range: 90 to 265 Vac Minimum Line frequency (fL): 47 Hz Regulated output voltage: 400 V Rated output power: 400 W Maximum 2fL output voltage ripple: 10 V pk-pk Hold-up time: 22 ms (VDROP after hold-up time: 300 V) Maximum switching frequency: 85 kHz (@Vin = 90 Vac, Pou t= 400 W) Minimum estimated efficiency: 90% (@Vin = 90 Vac, Pout = 400 W) Maximum ambient temperature: 50 C EMI: In acc. with

-630V 1 2 3 4 5 C7 330uF-450V +400Vdc +400Vdc NC RTN RTN +400Vout R3 100K R5 47R +400Vdc R9 R10 510k 510k R4 100K R102 C10 22N 0R0 D4 LL4148 R11 D5 BZX85-C18 510k R12 C13 220nF C11 C12 470nF/50V 100uF/50V R13 47K R36 3R9 12k C14 2.2uF R14 47k D7 LL4148 Q1 STP12NM50FP 1 2 3 4 INV VCC COMP GD MULT GND CS ZCD L6562A R17 6R8 8 7 R35 3R9 LL4148 D6 6 C15 68pF D8 LL4148 Q2 STP12NM50FP 5 R18 6R8 R15 1k8 R31 3k C16 120pF R16 30k R19 1K0 R32 R33 620k 620k Q3 BC857C C20 R34 C21 10k 10nF 330pF R101 0R0 2/9 Boost inductor spec. (Delta Electronics 86H-5410B): - vertical 6+6, PQ40+30 ferrite - 1 mm gap for 500 H primary inductance - Primary: 65 turns 30x0.2 mm - Secondary: 5 turns 0.28 mm R20 R21 0R47-1W 0R47-1W R22 0R47-1W R23 0R47-1W EVL6562A-400W 2 Circuit layout Circuit layout Figure 2. PCB layout(a) PFC PRECONDITIONER USING L6562A FOT a. Not in scale 3/9 Typical performance EVL6562A-400W 3 Typical performance Figure 3. EVL6562A-400W compliance to EN61000-3-2 standard @full load Measurements @