71321LA55PFG8 SRAM Chip Async Dual 5V 16K-bit 2K x 8 55ns 64-Pin TQFP T/R
From INTEGRATED DEVICE TECHNOLOGY
| Access Time | 55 |
| Access Time (Max) | 55ns |
| Address Bus | 22(b) |
| Architecture | Not Required |
| Clock Freq | Not Required(MHz) |
| Clock Freq (Max) | Not Required MHz |
| Density | 16384(Bit) |
| Function | MASTER |
| Mounting | Surface Mount |
| Number of I/O Lines | 16 |
| Number of Ports | 2 |
| Number of Words | 2K |
| Operating Supply Voltage (Max) | 5.5(V) |
| Operating Supply Voltage (Min) | 4.5(V) |
| Operating Supply Voltage (Typ) | 5(V) |
| Operating Temp Range | 0C to 70C |
| Operating Temperature Classification | Commercial |
| Package Type | TQFP |
| Packaging | Tape and Reel |
| Pin Count | 64 |
| Rad Hardened | No |
| Supply Current | 110 |
| Sync/Async | Asynchronous |
| Word Size | 8(b) |
