7130SA35JI SRAM Chip Async Dual 5V 8K-bit 1K x 8 35ns 52-Pin PLCC Tube
From INTEGRATED DEVICE TECHNOLOGY
| Access Time | 35 |
| Address Bus | 20(b) |
| Architecture | Not Required |
| Clock Freq | Not Required(MHz) |
| Density | 8192(Bit) |
| Function | MASTER |
| Mounting | Surface Mount |
| Number of I/O Lines | 16 |
| Number of Ports | 2 |
| Number of Words | 1K |
| Operating Supply Voltage (Max) | 5.5(V) |
| Operating Supply Voltage (Min) | 4.5(V) |
| Operating Supply Voltage (Typ) | 5(V) |
| Operating Temp Range | -40C to 85C |
| Operating Temperature Classification | Industrial |
| Package Type | PLCC |
| Packaging | Rail/Tube |
| Pin Count | 52 |
| Rad Hardened | No |
| Supply Current | 230 |
| Sync/Async | Asynchronous |
| Word Size | 8(b) |
